module DIVU(
input [:] dividend,
input [:] divisor,
input start,
input clock,
input reset,
output reg over,
output reg busy,
output [:] q,
output [:] r);
reg [:] count;
reg [:] reg_q;
reg [:] reg_r;
reg [:] reg_b;
reg r_sign;
wire [:] sub_add = r_sign?({reg_r,q[]} + {'b0,reg_b}):({reg_r,q[31]} - {1'b0,reg_b});
assign r = r_sign? reg_r + reg_b : reg_r;
assign q = reg_q;
always @ (posedge clock or posedge reset) begin
if (reset) begin
count <= ;
busy <= ;
over <= ;
end
else if (start)begin
reg_r <= ;
r_sign <= ;
reg_q <= dividend;
reg_b <= divisor;
count <= ;
busy <= ;
end
else if (busy) begin
reg_r <= sub_add[:];
r_sign <= sub_add[];
reg_q <= {reg_q[:],~sub_add[]};
count <= count +;
if(count == ) begin
busy <= ;
over <= ;
end
end
end
endmodule
module DIV(
input signed [:] dividend,
input signed [:] divisor,
input start,
input clock,
input reset,
output reg over,
output reg busy,
output [:] q,
output reg [:] r);
reg [:] count;
reg [:] reg_q;
reg [:] reg_r;
reg [:] reg_b;
reg r_sign;
wire [:] sub_add = r_sign?({reg_r,q[]} + {'b0,reg_b}):({reg_r,q[31]} - {1'b0,reg_b});
assign q = reg_q;
always @ (posedge clock or posedge reset)
if (reset) begin
count <= ;
busy <= ;
over <= ;
end
else begin
if (start) begin
reg_r <= ;
r_sign <= ;
if(dividend<)
reg_q <= -dividend;
else
reg_q <= dividend;
if(divisor<)
reg_b <= -divisor;
else
reg_b <= divisor;
count <= ;
busy <= ;
end
else if(busy) begin
if(count<=) begin
reg_r <= sub_add[:];
r_sign <= sub_add[];
reg_q <= {reg_q[:],~sub_add[]};
count <= count + ;
end
else begin
if(dividend[]^divisor[])
reg_q<=-reg_q;
if(!dividend[])
r<=r_sign? reg_r + reg_b : reg_r;
else
r<=-(r_sign? reg_r + reg_b : reg_r);
busy <= ;
over <= ;
end
end
end
endmodule
