I'm trying to set up a serial communication between the RPI and an FPGA. However, there is an issue when using the standard C library open() to init the serial interface: I'm using a scope to monitor what is sent and received via the RX and TX lines. A call to open causes the TX line of the RPI to go low for the length of one bit. I do not see this behavior with other computers/linux PCs. The point is, the FPGA assumes a valid transmission, since he thinks it's a start bit, but it's not.
我想在RPI和FPGA之间建立一个串行通信。但是，在使用标准的C库open()初始化串行接口时存在一个问题:我正在使用一个范围来监视通过RX和TX行发送和接收的内容。调用open会导致RPI的TX线在1位的长度上降低。我在其他计算机/linux pc上没有看到这种行为。关键是，FPGA假设一个有效的传输，因为他认为这是一个起始位，但它不是。
I checked with minicom installed on the RPI. Same thing. Starting minicom causes the TX line sending one bit. Once minicom has started, the communication runs as expected and all bytes have the correct frame size. Is there any way to suppress the TX line going low upon the open call to init the serial communication? Is this an expected behavior?
我在RPI上安装了minicom。同样的事情。启动minicom将导致TX行发送一个比特。一旦minicom启动，通信按预期运行，所有字节的帧大小都是正确的。是否有任何方法可以在打开调用初始化串行通信时抑制TX行?这是预期行为吗?
1 个解决方案
#1
1
This is a super far-fetched hunch, but this code seems a bit suspicious, from the pl011_startup() function in the PL011 serial port driver:
这是一个非常牵强的预感，但是这段代码看起来有点可疑，来自pl011_startup()函数中的PL011串口驱动程序:
/*
* Provoke TX FIFO interrupt into asserting.
*/
It seems as if it's twiddling the TX line when starting up the port, which would explain the pulse you're seeing. More investigation would surely be needed before concluding this is what happens, of course.
在启动端口时，它似乎在转动TX线，这就解释了你看到的脉冲。当然，在得出结论之前，还需要进行更多的调查。
So, I guess my "answer" boils down to: that sounds weird, perhaps it's something with the driver?
所以，我想我的“答案”可以归结为:这听起来很奇怪，也许是司机的问题?
Of course, one way of working around this is to apply some care in the FPGA end, assuming you have more control over it. "Proper" framing would take care of this, and make it clear that the spurious send can be discarded.
当然，解决这个问题的一种方法是在FPGA端应用一些注意事项，假设您对它有更多的控制。“适当的”框架会解决这个问题，并且清楚地表明伪造的发送可以被丢弃。
UPDATE: I meant that if "proper" messages were to be always framed by some sequence of bytes, the FPGA might be able to discard invalid ("unframed") data anyway, and thus become immune to the random pulse. For instance, messages could be defined to always start with SOH (start of header) or SOT (start of text) symbols (bytes with the values 0x01 and 0x02, respectively).
更新:我的意思是，如果“合适的”消息总是被一些字节序列框起来，那么FPGA可能会丢弃无效(“未框”)的数据，从而对随机脉冲免疫。例如，可以将消息定义为总是以SOH (header的开头)或SOT(文本的开头)符号(分别为0x01和0x02的字节)开头。
#1
1
This is a super far-fetched hunch, but this code seems a bit suspicious, from the pl011_startup() function in the PL011 serial port driver:
这是一个非常牵强的预感，但是这段代码看起来有点可疑，来自pl011_startup()函数中的PL011串口驱动程序:
/*
* Provoke TX FIFO interrupt into asserting.
*/
It seems as if it's twiddling the TX line when starting up the port, which would explain the pulse you're seeing. More investigation would surely be needed before concluding this is what happens, of course.
在启动端口时，它似乎在转动TX线，这就解释了你看到的脉冲。当然，在得出结论之前，还需要进行更多的调查。
So, I guess my "answer" boils down to: that sounds weird, perhaps it's something with the driver?
所以，我想我的“答案”可以归结为:这听起来很奇怪，也许是司机的问题?
Of course, one way of working around this is to apply some care in the FPGA end, assuming you have more control over it. "Proper" framing would take care of this, and make it clear that the spurious send can be discarded.
当然，解决这个问题的一种方法是在FPGA端应用一些注意事项，假设您对它有更多的控制。“适当的”框架会解决这个问题，并且清楚地表明伪造的发送可以被丢弃。
UPDATE: I meant that if "proper" messages were to be always framed by some sequence of bytes, the FPGA might be able to discard invalid ("unframed") data anyway, and thus become immune to the random pulse. For instance, messages could be defined to always start with SOH (start of header) or SOT (start of text) symbols (bytes with the values 0x01 and 0x02, respectively).
更新:我的意思是，如果“合适的”消息总是被一些字节序列框起来，那么FPGA可能会丢弃无效(“未框”)的数据，从而对随机脉冲免疫。例如，可以将消息定义为总是以SOH (header的开头)或SOT(文本的开头)符号(分别为0x01和0x02的字节)开头。