FPGA学习——按键控制LED流水灯（附源码 无按键消抖版本）
module key_led (
input wire clk,
input wire rst_n,
input wire [3:0] key,
output reg [3:0] led
);
parameter MAX = 10_000_000;
reg [23:0] cnt;
reg [1:0] cstate;
reg [3:0] flag;
//0.2s计数器
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
cnt <= 1'b0;
end
else if(cnt == MAX - 1'b1)begin
cnt <= 1'b0;
end
else begin
cnt <= cnt + 1'b1;
end
end
//状态控制 之所以不需要在状态计满后清零，是因为后续在计数至11后再加1值来到100
//而我们的状态设置为两位寄存器，因此只取后两位变为00，相当于清零
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cstate <= 2'd0;
end
else if(cnt == MAX - 1'b1)begin
cstate <= cstate + 1'b1;
end
else begin
cstate <= cstate;
end
end
//根据按键状态改变flag状态
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
flag <= 4'b0000;
end
else if(key[0] == 1'b0)begin
flag <= 4'b0001;
end
else if(key[1] == 1'b0)begin
flag <= 4'b0010;
end
else if(key[2] == 1'b0)begin
flag <= 4'b0100;
end
else if(key[3] == 1'b0)begin
flag <= 4'b1000;
end
else begin
flag <= flag;
end
end
//根据flag状态改变led状态
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
led <= 4'b0000;
end
else if(flag == 4'b0001)begin
case (cstate)
2'd0 : led <= 4'b0001;
2'd1 : led <= 4'b0010;
2'd2 : led <= 4'b0100;
2'd3 : led <= 4'b1000;
default: led <= 4'b0000;
endcase
end
else if(flag == 4'b0010)begin
case (cstate)
2'd0 : led <= 4'b1000;
2'd1 : led <= 4'b0100;
2'd2 : led <= 4'b0010;
2'd3 : led <= 4'b0001;
default: led <= 4'b0000;
endcase
end
else if(flag == 4'b0100)begin
case (cstate)
2'd0 : led <= 4'b1111;
2'd1 : led <= 4'b0000;
2'd2 : led <= 4'b1111;
2'd3 : led <= 4'b0000;
default: led <= 4'b0000;
endcase
end
else if(flag == 4'b1000)begin
case (cstate)
2'd0 : led <= 4'b1111;
2'd1 : led <= 4'b1111;
2'd2 : led <= 4'b1111;
2'd3 : led <= 4'b1111;
default: led <= 4'b0000;
endcase
end
else begin
led <= 4'b0000;
end
end
endmodule