verilog练习：8bit移位寄存器-2.代码

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output reg [7:0] q  
);

    wire [7:0] w_1;
    wire [7:0] w_2;
    wire [7:0] w_3;

    my_dff8 my_dff81 (.clk(clk), .d(d), .q(w_1));
    my_dff8 my_dff82 (.clk(clk), .d(w_1), .q(w_2));
    my_dff8 my_dff83 (.clk(clk), .d(w_2), .q(w_3));
    
    always @ (*) begin
        case (sel)
            2'b00: q <= d;
            2'b01: q <= w_1;
            2'b10: q <= w_2;
            2'b11: q <= w_3;
            default: q <= 8'b0;  
        endcase
    end
    
endmodule

​