相关公式：
1、
限制条件： ((B>=3)||(B = 1))&&(B>A)
2、 N = (P × B) + A
where P can be 2, 4, 8, 16, or 32
1)Prescaler,
The prescaler of the AD9520 allows for two modes of operation
管脚描述：
寄存器：
1、0x1E1<1:0> => 设置时钟源
Table 31 shows how the VCO, CLK, and VCO divider are selected. 0x1E1[1:0] selects the channel divider source and determines whether the VCO divider is used. It is not possible to select the VCO without using the VCO divider.
2、PLL Reference Inputs：Either a differential or a single-ended reference must be specifically enabled. All PLL reference inputs are off by default. The differential input and the single-ended inputs share two pins, REFIN (REF1)/REFIN (REF2). The desired reference input type is selected and controlled by 0x01C (see Table 49 and Table 53[DATASHEET]).
Crystal mode is nearly identical to differential mode. The user enables a maintaining amplifier by setting the Enable XTAL OSC bit, and putting a series resonant, AT fundamental cut crystal across the REFIN/REFIN pins.
Manual switchover is performed either through Register 0x01C or by using the REF_SEL pin.
3、Reference Divider R：The reference inputs are routed to the reference divider, R. R (a 14-bit counter) can be set to any value from 0 to 16,383 by writing to 0x011 and 0x012. (Both R = 0 and R = 1 give divide-by-1.)
注意事项: 1)The output of the R divider goes to one of the PFD inputs to be compared with the VCO frequency divided by the N divider. The frequency applied to the PFD must not exceed the maximumallowable frequency, which depends on the antibacklash pulse setting (see Table 2) .
2)It can also bereset by a SYNC operation.
4、VCO/VCXO Feedback Divider N: P, A, B, R
5、Table 31 shows how the VCO, CLK, and VCO divider are selected. 0x1E1[1:0] selects the channel divider source and determines whether the VCO divider is used. It is not possible to select the VCO without using the VCO divider
[黑色是用了的，灰色是没用的]
6、Either the internal VCO or the CLK can be selected as the source for the direct-to-output signal routing. To connect the LVPECL outputs directly to the internal VCO or CLK, the user must select the VCO divider as the source to the distribution section, even if no channel uses it.
7、Clock Frequency Division:
AD9520有一个VCO分频器，它对VCO输出进行1、 2、 3、4、 5或6分频，然后输入各通道分频器。 VCO分频器有两方面作用。一是将通道分频器的最大输入频率限制在 1.6GHz；二是让AD9520仅利用一个简单的后置分频器就能产生非常低的频率。 The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the VCO or CLK to the output is the product of the VCO divider (1, 2, 3, 4, 5, and 6) and the division of the channel divider.
VCO Divider ： The VCO divider provides frequency division between the internal VCO or the external CLK input and the clock distribution channel dividers. The VCO divider can be set to divide by 1, 2, 3, 4, 5, or 6 (see Table 56[DATASHEET], 0x1E0[2:0]).
Channel Dividers： A channel divider drives each group of three LVPECL outputs. There are four channel dividers (0, 1, 2, and 3) driving 12 LVPECL outputs (OUT0 to OUT11). Table 34 gives the register locations used for setting the division and other functions of these dividers. The division is set by the values of M and N. The divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit.
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
占空比为50%的限制条件： •偶数分频必须设置为M = N •奇数分频必须设置为M = N + 1
当未旁路或未被DCC功能校正时，各通道分频器输出的占空比为用百分数表示的数值(N + 1)/(N + M + 2)。
通道分频系数DX =(N + 1)+(M + 1) = N + M + 2。
配置实例：
1、
2、For internal VCO and clock distribution applications, the register settings shown in Table 22 should be used.
注意事项：
3、、For clock distribution applications where the external clock is <1600 MHz, the register settings shown in Table 23 should be used.
4、
配置EEPROM：
1、读、写状态及状态寄存器：During the data transfer process, the write and read registers via the serial port are generally not available except for one readback register, STATUS_EEPROM. To determine the data transfer state through the serial port in SPI mode, users can read the value of STATUS_EEPROM (1 = in process, and 0 = completed).
2、WRITING TO THE EEPROM：The EEPROM cannot be programmed directly through the serial port interface. To program the EEPROM and store a register setting file, do the following:
1). Program the AD9520 registers to the desired circuit state. If the user wants the PLL to lock automatically after power-up, the VCO calibration now bit (0x018[0]) must be set to 1. This allows VCO calibration to start automatically after register loading.
2).Program the EEPROM buffer registers, if necessary (see the Programming the EEPROM Buffer Segment section).
3).Set the enable EEPROM write bit (0xB02[0]) to 1 to enable the EEPROM.
4).Set the REG2EEPROM bit (0xB03[0]) to 1.
5).Set the IO_UPDATE bit (0x232[0]) to 1, which starts the process of writing data into the EEPROM to create the EEPROM setting file. This enables the AD9520 EEPROM controller to transfer the current register values, as well as the memory address and instruction bytes from the EEPROM buffer segment into the EEPROM. After the write process is completed, the internal controller sets 0xB03[0] (REG2EEPROM) back to 0. The readback register STATUS_EEPROM (0xB00[0]) is used to indicate the data transfer status between the EEPROM and the control registers (0 = done/inactive; 1 = in process/ active).At the beginning of the data transfer, STATUS_EEPROM is set to 1 by the EEPROM controller and cleared to 0 at the end of the data transfer. The user can access STATUS_EEPROM through the STATUS pin when the STATUS pin is programmed to monitor STATUS_EEPROM.
6). After the data transfer process is done (0xB00[0] = 0), set the enable EEPROM write register (0xB02[0]) to 0 to disable writing to the EEPROM.
*). To verify that the data transfer has completed correctly, the user can verify that 0xB01[0] = 0. A value of 1 in this register indicates a data transfer error.
3、READING FROM THE EEPROM
为验证数据传输已正确完成，用户可以检查0xB01[0]是否为0。如果此寄存器的值为1，则说明数据传输发生错误。
4、PROGRAMMING THE EEPROM BUFFER SEGMENT
一 般 而 言 ， 用 户 无 需 对 此 段 进 行 编 程 。
the EEPROM is only 512 bytes long. AD9520 EEPROM缓冲段长23字节，最多可以容纳7个寄存器段定义组。There are three operational codes: IO_UPDATE, end-of-data, and pseudo-end-of-data. It is important that the EEPROM buffer segment always have either an end-of-data or a pseudo-end-of-data operational code and that an IO_UPDATE operation code appear at least once before the end-of-data op code.
IO_UPDATE (Operational Code 0x80):
At a minimum, there should be at least one IO_UPDATE operational code after the end of the final register section definition group. 如果在写入EEPROM期间不存在此操作代码，则从EEPROM加载的寄存器值不会传输到活动寄存器空间，而且这些值在从EEPROM加载到AD9520之后不会生效。
End-of-Data (Operational Code 0xFF) :
EEPROM控制器使用此操作代码终止EEPROM与控制寄存器之间的数据传输过程。 EEPROM缓冲段中的最后一项应当是此操作代码或pseudo-end-ofdata操作代码。
Pseudo-End-of-Data (Operational Code 0xFE) :
如果用户希望定义7个以上的寄存器段定义组，则可以使用 pseudo-end-of-data操作代码。当 EEPROM控制器接收到pseudo-end-of-data操作代码时，它会暂停数据传输过程，将REG2EEPROM位清零，并使能AD9520串行端口。然后，用户可以再次对EEPROM缓冲 段 进 行 编 程 ， 并 将 R E G 2 E E P R O M位 ( 0 x B 0 3 ) 和IO_UPDATE寄存器(0x232)置1，重新启动数据传输过程。
管脚的作用效果：
配置尝试：
目标：fref = 10Mhz,fout = 70Mhz;
配置： 1).fvco = 2800Mhz
2).VCO分频系数=4；Dx = 10 => [M = 4, N = 4]
3).P = 1 (FD) , B = 280, A = 0
寄存器设置：
通过Quad SPI核来配置：
能看到STATUS引脚在更新指令（232<1>）发出后，开始被设为N分频器的输出。
黄色时间轴右侧为VCO的校准指令（018<0>232<1>,018<1>232<1>）。
代码：
v0.01
配的凑合，勉强能用
还没和ADC配合起来。
配置期间出现出现了很奇怪的bug:
1.IO分配转换成的xdc不全，导致io分配的信息在下次综合时丢失=>解决方案：多备份吧。
2、稍作更改后SPI核不工作，可能原因：diagram画完后忘记生成wrapper和output。
问题解决：是sdk里的static的原因。对static理解不足，被绊了一下。
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v0.02
和AD9265一起使用。
左下的是AD9520的spi配置过程，右边是AD9265的SPI配置过程。
上方的三个AD9520的信号显示了AD9520工作正常。
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参考资料:
[1]蔡春霞,吴琼之.AD9520高速时钟发生器在5Gs/s数据采集系统中的应用[J].电子设计工程,2011,19(16):170-173.
[2]AD9520_DATASHEET_英文版
[3]AD9520_DATASHEET_中文版 [https://download.csdn.net/download/u012135070/10482716]