信号监测---verilog
此模块用于监测某一信号源是否持续稳定的传送。
监测思路：监测信号源高电平或者低电平的宽度是否始终保持一致（一定范围内允许有误差）
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2018/10/12 14:43:57
// Design Name:
// Module Name: signal_detection
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module signal_detection #(
parameter WIDTH = ,
parameter MAXIMUM_ERROR = ,
parameter CNT_CLK_FREQUENCY = ,
parameter DELAY_SIGNAL_OUT = ,
parameter TOTAL_TIME_HIGH = ,
parameter TOTAL_TIME_LOW =
)
(
input wire clk ,
input wire clk_out_syn ,
input wire rst ,
input wire signal_src ,
output wire lock
); //---------------------------------------------------------------------- // Signal source synchronization reg signal_src_delay_1 = ;
reg signal_src_delay_2 = ; always @(posedge clk or posedge rst)
begin
if(rst)
begin
signal_src_delay_1 <= 'b0 ;
signal_src_delay_2 <= 'b0 ;
end
else
begin
signal_src_delay_1 <= signal_src ;
signal_src_delay_2 <= signal_src_delay_1 ;
end
end //---------------------------------------------------------------------- //Rising edge detection assign rising_edge = signal_src_delay_1 && (!signal_src_delay_2) ;
assign falling_edge = (!signal_src_delay_1) && signal_src_delay_2 ; //---------------------------------------------------------------------- //count enable 信号上升沿开始计数，下降沿停止计数，此模块采用的是计算高电平的宽度 reg cnt_en = ; always @(posedge clk or posedge rst)
begin
if(rst)
cnt_en <= 'b0 ;
else if(rising_edge)
cnt_en <= 'b1 ;
else if(falling_edge)
cnt_en <= 'b0 ;
end //---------------------------------------------------------------------- //count clock period reg [:] cnt = ; always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= 'd0 ;
else if(cnt_en)
cnt <= cnt + 'b1 ;
else
cnt <= 'd0 ;
end //---------------------------------------------------------------------- //total 存储两个相邻高电平的宽度 reg [:] total_number = ;
reg [:] total_number_delay = ;
reg [:] total_number_delay_1 = ;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
total_number <= 'd0 ;
total_number_delay <= 'd0 ;
total_number_delay_1 <= 'd0 ;
end
else if(falling_edge)
begin
total_number <= cnt ;
total_number_delay <= total_number ;
total_number_delay_1 <= total_number_delay ;
end
else if(get_total_time_high || get_total_time_low)
begin
total_number <= 'd0 ;
total_number_delay <= 'd0 ;
total_number_delay_1 <= 'd0 ; end
end
//此处或得了相邻三个高电平的宽度值
//---------------------------------------------------------------------- localparam UNLOCK = 'b0;
localparam LOCK = 'b1; //---------------------------------------------------------------------- wire lock_state_1 ;
wire lock_state_2 ;
//考虑高电平宽度误差量
assign lock_state_1 = (total_number >= total_number_delay_1) && ((total_number - total_number_delay_1) <= MAXIMUM_ERROR) && (total_number > 'd100) ;
assign lock_state_2 = (total_number < total_number_delay_1) && ((total_number_delay_1 - total_number) <= MAXIMUM_ERROR) && (total_number > 'd100) ;
//用total_number 与 total_number_delay_1 两个值来参与运算，是考虑到了隔行视频，相邻两个高电平的宽度是不一样的，因为一帧有两场，即一帧中有两个V信号的有效区间
//---------------------------------------------------------------------- // 1us reg get_time_1us ;
reg [WIDTH-:] m ;
always @ ( posedge clk or posedge rst )
begin
if( rst )
begin
get_time_1us <= 'b0;
m <= ;
end
else if( m == CNT_CLK_FREQUENCY - )
begin
get_time_1us <= 'b1;
m <= ;
end
else
begin
get_time_1us <= 'b0;
m <= m + 'b1;
end
end //---------------------------------------------------------------------- reg get_total_time_high ;
reg get_total_time_low ;
reg [WIDTH-:] i ;
reg [WIDTH-:] k ; always @ (posedge clk or posedge rst)
begin
if(rst)
begin
get_total_time_high <= 'b0 ;
get_total_time_low <= 'b0 ;
i <= ;
k <= ;
end else
begin
get_total_time_high <= 'b0 ;
get_total_time_low <= 'b0 ; if(signal_src_delay_2 == 'b0)
begin
if( i == TOTAL_TIME_LOW - )
begin
get_total_time_low <= 'b1 ;
i <= ;
end else if(get_time_1us)
i <= i + 'b1 ;
end else
i <= ; if(signal_src_delay_2 == 'b1)
begin
if( k == TOTAL_TIME_HIGH - )
begin
get_total_time_high <= 'b1 ;
k <= ;
end else if(get_time_1us)
k <= k + 'b1 ;
end else
k <= ;
end
end //---------------------------------------------------------------------- reg current_state ;
reg next_state ; always @ ( posedge clk or posedge rst )
begin
if( rst )
current_state <= UNLOCK;
else
current_state <= next_state;
end //---------------------------------------------------------------------- always @ ( * )
begin
case( current_state )
UNLOCK:
if( lock_state_1 || lock_state_2 )
next_state = LOCK;
else
next_state = UNLOCK;
LOCK:
if( get_total_time_high || get_total_time_low )
next_state = UNLOCK;
else
next_state = LOCK;
endcase
end //---------------------------------------------------------------------- //output reg reg lock_r; always @ (posedge clk or posedge rst)
begin
if(rst)
lock_r <= 'b0 ; else
begin
case(current_state)
UNLOCK: lock_r <= 'b0;
LOCK : lock_r <= 'b1;
endcase
end
end reg dly_reg[:DELAY_SIGNAL_OUT-]; genvar var_i;
generate
for (var_i=;var_i<=DELAY_SIGNAL_OUT-;var_i=var_i+)
begin:delay_generate_block
if (var_i==)
begin
always @ (posedge clk_out_syn or posedge rst)
if (rst)
dly_reg[var_i] <= ;
else
dly_reg[var_i] <= lock_r;
end
else
begin
always @ (posedge clk_out_syn or posedge rst)
if (rst)
dly_reg[var_i] <= ;
else
dly_reg[var_i] <= dly_reg[var_i-];
end
end
endgenerate assign lock = dly_reg[DELAY_SIGNAL_OUT-]; endmodule
仿真结果：
