文件名称：AD9854 300M DDS数据手册
文件大小：435KB
文件格式：PDF
更新时间：2016-09-20 05:28:13
ad9854
AD9854 300M DDS数据手册 300 MHz Internal Clock Rate Integrated 12-Bit Output DAC Ultrahigh-Speed, 3 ps RMS Jitter Comparator Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz (61 MHz) AOUT 43 to 203 Programmable Reference Clock Multiplier Dual 48-Bit Programmable Frequency Registers Dual 14-Bit Programmable Phase Offset Registers 12-Bit Amplitude Modulation and Programmable Shaped On/Off Keying Function Single Pin FSK and PSK Data Interface Linear or Nonlinear FM Chirp Functions with Single Pin Frequency “Hold” Function Frequency-Ramped FSK <25 ps RMS Total Jitter in Clock Generator Mode Automatic Bidirectional Frequency Sweeping SIN(x)/x Correction Simplified Control Interface 10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or 100 MHz Parallel 8-Bit Programming