文件名称：NDI_Dec.zip
文件大小：401KB
文件格式：ZIP
更新时间：2023-07-28 02:42:51
NDI FPGA DEC
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library NDI_Dec; use NDI_Dec.NDI_Pkg.all; component Dec_Core_E is generic ( CORE_ID : integer := 0; VID_ADDR_WIDTH : integer := 32; VID_BURST_WIDTH : integer := 8; VID_BURST_LENGTH : integer := 8; NDI_ADDR_WIDTH : integer := 32; NDI_BURST_WIDTH : integer := 8; NDI_BURST_LENGTH : integer := 8 ); port ( -- Register interface reg_clk : in std_logic; reg_reset : in std_logic; reg_irq : out std_logic; reg_irq_ena : out std_logic; RegWr_addr : in unsigned(5 downto 0); RegWr_data : in DWORD_T; RegWr_we : in std_logic; RegWr_be : in std_logic_vector(3 downto 0); RegRd_addr : in unsigned(5 downto 0); RegRd_data : out DWORD_T; RegRd_rden : in std_logic; -- NDI interface ndi_clk : in std_logic; ndi_rst : in std_logic; -- Read Interface (compressed NDI data) ndir_wait_n : in std_logic := '0'; ndir_addr : out std_logic_vector(NDI_ADDR_WIDTH - 1 downto 0); ndir_rvalid : in std_logic := '0'; ndir_rdata : in std_logic_vector(63 downto 0) := (others=>'0'); ndir_read : out std_logic; ndir_burstcount : out std_logic_vector(NDI_BURST_WIDTH - 1 downto 0); -- Write Interface (raw video) vidw_wait_n : in std_logic; vidw_addr : out std_logic_vector(VID_ADDR_WIDTH - 1 downto 0); vidw_wdata : out QWORD_T; vidw_write : out std_logic; vidw_burstcount : out std_logic_vector(VID_BURST_WIDTH - 1 downto 0); vidw_byteenable : out std_logic_vector(7 downto 0) ); end component;
【文件预览】：
NDI_Dec
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