文件名称：NDI_Enc.zip
文件大小：303KB
文件格式：ZIP
更新时间：2023-07-28 02:41:52
NDI FPGA VHDL
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library NDI_Enc; use NDI_Enc.NDI_Pkg.all; component Enc_Core_E is generic ( CORE_ID : integer := 0; DEBUG : integer := 0; AVL_ADDR_WIDTH : integer := 32; AVL_BURST_WIDTH : integer := 8 ); port ( -- Register interface reg_clk : in std_logic; reg_reset : in std_logic; reg_irq : out std_logic; reg_irq_ena : out std_logic; RegWr_addr : in unsigned(5 downto 0); RegWr_data : in DWORD_T; RegWr_we : in std_logic; RegWr_be : in std_logic_vector(3 downto 0); RegRd_addr : in unsigned(5 downto 0); RegRd_data : out DWORD_T; RegRd_rden : in std_logic; -- NDI interface ndi_clk : in std_logic; ndi_rst : in std_logic; -- Read Interface (Uncompressed Video) vidr_wait_n : in std_logic; vidr_addr : out std_logic_vector(AVL_ADDR_WIDTH - 1 downto 0); vidr_rvalid : in std_logic; vidr_rdata : in QWORD_T; vidr_read : out std_logic; vidr_burstcount : out std_logic_vector(AVL_BURST_WIDTH - 1 downto 0); vidr_byteenable : out std_logic_vector(7 downto 0); -- Write Interface (Compressed NDI) ndiw_wait_n : in std_logic; ndiw_addr : out std_logic_vector(AVL_ADDR_WIDTH - 1 downto 0); ndiw_wdata : out QWORD_T; ndiw_write : out std_logic; ndiw_burstcount : out std_logic_vector(AVL_BURST_WIDTH - 1 downto 0); ndiw_byteenable : out std_logic_vector(7 downto 0) ); end component;
【文件预览】：
NDI_Enc
----Encode_Xilinx.vhdp(168KB)
----Encode_Altera.vhd(171KB)
----Encode_Altera.lic(413B)
----Encode_x4.vhd(15KB)
----Enc_Core_Comp.vhd(2KB)