【文件属性】：
文件名称：ad9850工作原理及设计
文件大小：112KB
文件格式：PDF
更新时间：2013-05-18 08:26:48
ad9850设计
FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40 MHz AOUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel Byte or Serial
Loading Format
Phase Modulation Capability
+3.3 V or +5 V Single Supply Operation
Low Power: 380 mW @ 125 MHz (+5 V)
Low Power: 155 mW @ 110 MHz (+3.3 V)
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase–Agile Sine-Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications