AES:Verilog中的AES实施

【文件属性】：
文件名称：AES:Verilog中的AES实施
文件大小：194KB
文件格式：ZIP
更新时间：2021-05-09 18:50:09
SystemVerilog AES Verilog中的AES实施 这是Vivado 2016.4项目。

【文件预览】：
AES-master
----aes_pipeline_stage8.sv(2KB)
----testbench.sv(3KB)
----fn_aes_encrypt_stage.sv(13KB)
----aes_pipeline_stage3.sv(2KB)
----scratch()
--------timing_report_aes_gcm_128_input_impl.txt(369KB)
--------timing_report_aes_gcm_128_input_pipeline_impl.txt(377KB)
--------timing_report_aes_gcm_128_input_five_pipelines_synth.txt(296KB)
--------timing_report_aes_gcm_128_input_pipeline_synth.txt(389KB)
--------timing_report_aes_gcm_128_input_two_pipelines_impl.txt(332KB)
--------timing_report_aes_gcm_128_input_two_pipelines_synth.txt(322KB)
--------timing_report_aes_gcm_128_input_synth.txt(382KB)
--------timing_report_state3.txt(160KB)
--------temp_utilization_report.txt(7KB)
--------timing_report_state3_aes_path.txt(264KB)
--------timing_report.txt(605KB)
--------timing_report_aes_gcm_128_input_five_pipelines_impl.txt(291KB)
----aes.sv(2KB)
----aes_pipeline_stage2.sv(2KB)
----aes_pipeline_stage5.sv(2KB)
----constraints_artix_7.xdc(3KB)
----fn_aes_key_expansion.sv(5KB)
----display.sv(3KB)
----clk_gen.sv(3KB)
----aes_pipeline_stage4.sv(2KB)
----simulate.tcl(91B)
----README.md(70B)
----compile.tcl(246B)
----gcm_aes.sv(8KB)
----aes_pipeline_stage6.sv(2KB)
----aes_pipeline_stage7.sv(2KB)
----fn_aes_ghash_multiplication.sv(457B)
----.gitignore(91B)
----aes_pipeline_stage1.sv(2KB)
----build_project.tcl(2KB)