文件名称：数据冒险load-use-一道关于存储的详解题
文件大小：662KB
文件格式：PPT
更新时间：2024-05-12 07:15:15
题目
数据冒险2（load-use） Clock Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 I0: Load Plus 1 Plus 2 R-Type （采用寄存器前半写后半读，不转发） 如果第1条指令为load，且目标是写入寄存器R 则随后的第2、3条指令使用R时都会发生数据冒险 再后的第4条及之后的指令都不会发生冒险 Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr * Similarly, although the load instruction is fetched during cycle 1, the data is not written into the register file until the end of Cycle 5. Consequently, the earliest time we can read this value from the register file is in Cycle 6. In other words, there is a 3-instruction delay between the load instruction and the instruction that can use the result of the load. This is referred to as Data Hazard in the text book. We will show in the next lecture that by clever design techniques, we can reduce this delay to ONE instruction. That is if the load instruction is issued in Cycle 1, the instruction comes right next to it (Plus 1) cannot use the result of this load but the next-next instruction (Plus 2) can. +2 = 73 min. (Y:53)