文件名称：MAXII实现串口通讯
文件大小：76KB
文件格式：ZIP
更新时间：2024-09-09 07:22:26
FPGA
MAXII实现串口通讯Verilog代码
【文件预览】：
uart
----uart_top.pof(8KB)
----speed_select.v.bak(195B)
----uart_top.qws(48B)
----uart_top.flow.rpt(8KB)
----my_uart.bdf(9KB)
----uart_top.fit.summary(377B)
----uart_top.fit.rpt(59KB)
----uart_tx.v.bak(507B)
----uart_tx.v(2KB)
----db()
--------uart_top.db_info(153B)
--------prev_cmp_uart_top.qmsg(36KB)
--------uart_top.sld_design_entry.sci(211B)
--------logic_util_heursitic.dat(4KB)
----uart_tx.bsf(2KB)
----uart_top.eda.rpt(6KB)
----uart_top.qpf(1KB)
----uart_rx.v.bak(191B)
----simulation()
--------modelsim()
----speed_select.v(625B)
----uart_rx.bsf(2KB)
----uart_top.v(2KB)
----uart_top_assignment_defaults.qdf(56KB)
----incremental_db()
--------compiled_partitions()
--------README(653B)
----uart_top.sta.summary(401B)
----uart_top.sta.rpt(57KB)
----uart_top.map.summary(317B)
----uart_rx.v(2KB)
----uart_top.pin(15KB)
----uart_top.v.bak(124B)
----uart_top.fit.smsg(334B)
----uart_top.asm.rpt(7KB)
----uart_top.cdf(382B)
----uart_top.map.rpt(23KB)
----speed_select.bsf(2KB)
----uart_top.qsf(3KB)
----uart_top.done(26B)