文件名称：8-by-8 Bit Shift Add Multiplier
文件大小：2.03MB
文件格式：PDF
更新时间：2021-03-28 16:23:59
乘法器 multiplier
The objective of this project is to go through a design cycle from initial conception to simulation. In this case, it has been taken several steps further and synthesis as well as place & route was also achieved. The goal is to design and simulate an 8-by-8 bit shift/add multiplier. The result is a completely synthesized 8-by-8 bit and 32-by-32 bit shift/add multiplier with various design options for speed and area.