文件名称：基于FPGA的VGA显示
文件大小：4.34MB
文件格式：PDF
更新时间：2014-12-12 04:14:31
fpga vga
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity russia is port(clk:in std_logic; reset:in std_logic; left:in std_logic; right:in std_logic; scores:out integer range 0 to 15; sta0:out std_logic_vector(0 to 3); sta1:out std_logic_vector(0 to 3); sta2:out std_logic_vector(0 to 3); sta3:out std_logic_vector(0 to 3)); end russia;