文件名称：Verilog Simulation Guide
文件大小：362KB
文件格式：PDF
更新时间：2015-11-26 14:34:38
Verilog
Cadence VHDL/Verilog Simulation Guide and Tutorial, This guide describes, via a tutorial, how to set up the personal environment,variables), and simulate VHDL (or Verilog) models using the Cadence tools.