文件名称：UART_RAM_VHDL
文件大小：239KB
文件格式：ZIP
更新时间：2016-11-30 15:32:35
UART RAM
UART RAM VHDL Modelsim仿真工程 QuartusII工程
【文件预览】：
UART
----QuartusII()
--------uart_ram.eda.rpt(6KB)
--------uart_ram.flow.rpt(9KB)
--------uart_ram.map.summary(466B)
--------uart_ram_nativelink_simulation.rpt(999B)
--------db()
--------simulation()
--------uart_ram.asm.rpt(7KB)
--------uart_ram.done(26B)
--------incremental_db()
--------uart_ram.qpf(1KB)
--------dual_port_ram.cmp(1KB)
--------uart_ram.sof(148KB)
--------uart_ram.sta.summary(2KB)
--------greybox_tmp()
--------uart_ram.fit.summary(602B)
--------uart_ram.fit.rpt(152KB)
--------uart_ram.fit.smsg(513B)
--------uart_ram.sta.rpt(673KB)
--------uart_ram.pin(26KB)
--------dual_port_ram.vhd(10KB)
--------uart_ram.qsf(4KB)
--------uart_ram.map.rpt(55KB)
--------dual_port_ram.qip(292B)
--------uart_ram.pof(512KB)
----ModelsimSE1()
--------testbench.vhd(7KB)
--------uart_rx.vhd(10KB)
--------uart.vhd(7KB)
--------run.do(1KB)
--------uart_tx.vhd(8KB)
--------baud_clk_gen.vhd(3KB)
----ModelsimSE()
--------testbench.vhd(6KB)
--------uart_rx.vhd(10KB)
--------uart.vhd(7KB)
--------run.do(1KB)
--------uart_tx.vhd(8KB)
--------baud_clk_gen.vhd(3KB)
--------uart_rx1.vhd(10KB)
----VHDL()
--------uart_ram.vhd.bak(9KB)
--------uart_rx.vhd.bak(10KB)
--------write_ram.vhd(7KB)
--------uart_rx.vhd(10KB)
--------uart.vhd(7KB)
--------uart_ram.vhd(10KB)
--------uart_tx.vhd(8KB)
--------read_ram.vhd.bak(6KB)
--------baud_clk_gen.vhd(3KB)
--------baud_clk_gen.vhd.bak(3KB)
--------read_ram.vhd(6KB)
--------uart_rx1.vhd(10KB)
--------write_ram.vhd.bak(6KB)