文件名称：complex clock gating with integrated clock gating logic cell
文件大小：506KB
文件格式：PDF
更新时间：2013-05-18 09:21:16
clock gating ICG
Clock gating is an effective technique for minimizing dynamic power in sequential circuits. Applying clock-gating at gate-level not only saves time compared to implementing clock-gating in the RTL code but also saves power and can easily be automated in the synthesis process. This paper presents simulation results on various types of clock-gating at different hierarchical levels on a Serial Peripheral Interface (SPI) design. In general power savings of about 30% and 36% reduction on toggle rate can be seen with different complex clockgating methods with respect to no clock-gating in the design. Index terms-- Automated synthesis