文件名称:fpga程序关于sjtag
文件大小:17KB
文件格式:V
更新时间:2014-06-01 10:50:49
fpga
virelog硬件程序module sjtag_fpga_core ( clk96_o, // will change to 24MHz clock reset_n, // push button? jtag_tck, jtag_mode, jtag_tdi, jtag_tdo,
文件名称:fpga程序关于sjtag
文件大小:17KB
文件格式:V
更新时间:2014-06-01 10:50:49
fpga
virelog硬件程序module sjtag_fpga_core ( clk96_o, // will change to 24MHz clock reset_n, // push button? jtag_tck, jtag_mode, jtag_tdi, jtag_tdo,