文件名称：verilog语言的任意分频
文件大小：818B
文件格式：TXT
更新时间：2014-04-12 13:31:00
verilog分频
module clk_div(clk_sys, rst, clk_out，div_num); input clk_sys; input rst; input [4:0] div_num; output clk_out; reg clk_out; reg [3:0] baud_count; always @(posedge clk_sys) begin if (rst) begin baud_count<=0; clk_out<=0; end else begin if (baud_count==(div_num/2)-1) begin baud_count<=0; clk_out<=~clk_out; end else begin baud_count<=baud_count+1; clk_uart<= clk_out; end end end endmodule