【文件属性】：
文件名称：Attacking Constraint Complexity in Verification IP Reuse
文件大小：201KB
文件格式：PDF
更新时间：2013-01-03 07:30:34
Attacking Constraint Complexity in Verification
As chip design becomes larger and more complex, verification engineers are expanding constrained-random testing to meet the validation demand. The size and complexity of constraint problems are growing, resulting in performance and capacity issues. This paper discusses the key challenges verification engineers face when writing constraints – how to achieve test goals, how to optimize constraints for performance and how to manage the interaction and code complexity. We use two case studies from the network domain to illustrate these issues.