文件名称：CALCULATING SETTLING TIME FOR SWITCHED CAPACITOR ADCS
文件大小：227KB
文件格式：PDF
更新时间：2016-01-21 02:49:23
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Many of Silicon Lab’s devices feature an on-chip SAR analog-to-digital converter (ADC). These ADC’s use a sample capacitor that is charged to the voltage of the input signal that is used by the SAR logic to perform its data conversion. Due to the ADC’s sample capacitance, input impedance, and the external input circuitry, there will be a settling time required for the sample capacitor to assume the measured input signal voltage. This application note describes a method for calculating the required settling time for good ADC measurements and methods to achieve meeting settling time requirements.