文件名称：mini aes 128bit
文件大小：480KB
文件格式：GZ
更新时间：2018-03-02 04:25:35
aes
Simple AES/Rijndael IP Core. I have tried to create a implementation of this standard that would fit in to a low cost FPGA, like the Spartan IIe series from Xilinx, and still would provide reasonably fast performance. This implementation is with a 128 bit key expansion module only. Implementations with different key sizes (192 & 256 bits) and performance parameters (such as a fully pipelined ultra-high -speed version) are commercially available from ASICS.ws (www.asics.ws). This document will describe the interface to the IP core. It will not talk about the AES standard itself.
【文件预览】：
mini_aes
----web_uploads()
----tags()
--------INITIAL()
----trunk()
--------source()
--------LICENSE.txt(2KB)
--------bench()
--------doc()
--------data()
--------README(637B)
----branches()