文件名称：Hardware Design Based on Verilog HDL
文件大小：781KB
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更新时间：2012-05-27 05:23:20
Hardware Design Based on Verilog
Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classi ed under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal veri cation. This thesis proposes a uni ed approach to hardware design in which both simulation and formal veri cation can co-exist. Relational Duration Calculus (an extension of Duration Calculus) is developed and used to de ne the formal semantics of Verilog HDL (a standard industry hardware description language). Relational Duration Calculus is a temporal logic which can deal with certain issues raised by the behaviour of typical hardware description languages and which are hard to describe in a pure temporal logic. These semantics are then used to unify the simulation of Verilog programs, formal veri cation and the use of algebraic laws during the design stage. A simple operational semantics based on the simulation cycle is shown to be isomorphic to the denotational semantics. A number of laws which programs satisfy are also given, and can be used for the comparison of syntactically different programs. The thesis also presents a number of other results. The use of a temporal logic to specify the semantics of the language makes the development of programs which satisfy real-time properties relatively easy. This is shown in a case study. The fuzzy boundary in interpreting Verilog programs as either hardware or software is also exploited by developing a compilation procedure to translate programs into hardware. Hence, the two extreme interpretations of hardware description languages as software, with sequential composition as the topmost operator (as in simulation), and as hardware with parallel composition as the topmost operator are exposed. The results achieved are not limited to Verilog. The approach taken was carefully chosen so as to be applicable to other standard hardware description languages such as VHDL.