RESEARCH AND DESIGN OF LOW JITTER, WIDE LOCKING-RANGE

时间:2015-07-24 10:37:41
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文件名称:RESEARCH AND DESIGN OF LOW JITTER, WIDE LOCKING-RANGE

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更新时间:2015-07-24 10:37:41

PLL DLL digital

PHASE-LOCKED loops (PLLs) and delay-locked loops (DLLs) are often used in integrated circuits in order to compensate for clock distribution delays and to improve overall system timing. PLLs are also widely used in clock recovery and frequency synthesis. When compared to traditional implementations of PLLs and DLLs, an all-digital approach will be found more suitable for monolithic implementation on the same die with other digital circuits. A robust, process-independent performance is expected using all digital techniques.


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