Chip Multiprocessor Architecture Techniques to Improve Throughput and Latency

时间:2021-05-18 02:29:00
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文件名称:Chip Multiprocessor Architecture Techniques to Improve Throughput and Latency

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更新时间:2021-05-18 02:29:00

多处理器技术

多处理器架构技术的介绍文档。Chip multiprocessors — also called multi-core microprocessors or CMPs for short — are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today’s processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today’s microprocessor chips, it is too costly to design and debug ever-larger processors every year or two.


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