文件名称：AD转换控制模块.txt
文件大小：4KB
文件格式：TXT
更新时间：2023-01-16 02:20:43
VHDL quartusII A\D转换控制
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADZHKZ IS PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); RST:IN STD_LOGIC; CLK:IN STD_LOGIC; EOC:IN STD_LOGIC; ALE:OUT STD_LOGIC; START:OUT STD_LOGIC; OE:OUT STD_LOGIC; ADDA:OUT STD_LOGIC; BCDOUT: OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); END ENTITY ADZHKZ; ARCHITECTURE ART OF ADZHKZ IS TYPE STATES IS (ST0,ST1,ST2,ST3,ST4,ST5,ST6); SIGNAL CURRENT_STATE,NEXT_STATE:STATES; SIGNAL REGL:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK0,LOCK1:STD_LOGIC; SIGNAL VALUE:STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL CEN:STD_LOGIC; SIGNAL ALE0: STD_LOGIC; SIGNAL START0:STD_LOGIC; SIGNAL OE0:STD_LOGIC; BEGIN STATESYSTEM:BLOCK IS BEGIN ADDA<='1'; PRO:PROCESS(CURRENT_STATE,EOC) IS 部分