文件名称：DE2官方文件
文件大小：133KB
文件格式：RAR
更新时间：2020-10-19 06:24:20
DE2; FPGA; verilog
This VHDL/Verilog or C/C++ source code is intended as a design reference which illustrates how these types of functions can be implemented. It is the user's responsibility to verify their design for consistency and functionality through the use of formal verification methods. Terasic provides no warranty regarding the use or functionality of this code.
【文件预览】：
DE2_TV_New_v1
----PLL.v(13KB)
----TD_Detect.v(647B)
----VGA_Ctrl.v(3KB)
----Sdram_Control_4Port()
--------Sdram_PLL.v(16KB)
--------Sdram_RD_FIFO.v(8KB)
--------sdr_data_path.v(909B)
--------Sdram_PLL.ppf(416B)
--------command.v(17KB)
--------Sdram_Params.h(2KB)
--------Sdram_WR_FIFO.v(8KB)
--------control_interface.v(6KB)
--------Sdram_Control_4Port.v(15KB)
----I2C_Controller.v(4KB)
----SEG7_LUT.v(705B)
----DIV.v(4KB)
----DE2_TV.sof(821KB)
----ITU_656_Decoder.v(3KB)
----DE2_TV.qpf(944B)
----AUDIO_DAC.v(9KB)
----MAC_3.v(14KB)
----DE2_TV.pof(2MB)
----I2C_AV_Config.v(5KB)
----YUV422_to_444.v(734B)
----DE2_TV.v(19KB)
----YCbCr2RGB.v(3KB)
----SEG7_LUT_8.v(458B)
----TP_RAM.v(8KB)
----Reset_Delay.v(497B)
----Line_Buffer.v(4KB)
----DE2_TV.qsf(25KB)