文件名称：Computing_DDR3L_H5TC4G4
文件大小：492KB
文件格式：PDF
更新时间：2020-11-06 08:42:43
DDR3 SK hynix 4Gb
SK DDR3 主要的timing及部分feature介绍，total35 page Description The H5TC4G43AFR-xxA, H5TC4G83AFR-xxA and H5TC4G63AFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD infor mation for details.) SK hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.