文件名称：verilog的布斯乘法器
文件大小：22KB
文件格式：7Z
更新时间：2014-11-30 13:11:09
布斯乘法器 verilog
verilog的布斯乘法器daima entity booth16 is port ( rst: in std_logic; -- active high; to reset the system clk: in std_logic; go: in std_logic;-- if go rises from ‘0’ to ‘1’, multiplier starts operation y: in std_logic_vector(15 downto 0); x: in std_logic_vector(15 downto 0); o: out std_logic_vector(30 downto 0); done: out std_logic – if done is ‘1’, the operation completes and o is ready ); end booth16;
【文件预览】：
multi
----vsim.wlf(40KB)
----multi.cr.mti(409B)
----16_multi.v.bak(2KB)
----test_multi.v(557B)
----work()
--------test_booth()
--------test_mul()
--------_info(806B)
--------booth()
--------mul()
----transcript(419B)
----multi.mpf(24KB)
----test_multi.v.bak(557B)
----vish_stacktrace.vstf(3KB)
----16_multi.v(2KB)