文件名称：A 10-Gb/s CMOS Clock and Data Recovery Circuit
文件大小：227KB
文件格式：PDF
更新时间：2013-11-15 03:57:22
Clock recovery half-rate CDR optical
This paper describes the design of the first 10-Gb/s CMOS clock and data recovery (CDR) circuit. A linear phase detector (PD) is introduced that compares the phase of the incoming data with that of a half-rate clock. The CDR circuit also incorporates a three-stage interpolating ring oscillator to achieve a wide tuning range.