文件名称：ASIC设计前端经典
文件大小：40.89MB
文件格式：RAR
更新时间：2018-01-05 05:06:09
ASIC设计前端经典
ASIC设计前端经典
【文件预览】：
ASIC前端经典.txt
Principles_of_Verifiable_RTL_Design_Second_Edition_-_A_Functional_Coding_Style_Supporting_Verification_Processes_in_Verilog.rar
A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.rar
(Kluwer) Writing Testbenches--Functional Verification of HDL Models.rar
Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design.Compiler.Physical.Compiler.And.Primetime.rar