文件名称：Verilog_coding_style_guidelines.pdf
文件大小：69KB
文件格式：PDF
更新时间：2012-06-30 18:41:38
verilog
The blocking assignment operator is an equal sign ("="). A blocking assignment gets its name because a blocking assignment must evaluate the RHS arguments and complete the assignment without interruption from any other Verilog statement. The assignment is said to "block" other assignments until the current assignment has completed. The one exception is a blocking assignment with timing delays