文件名称：isscc2018 高精度ADC一章详细ppt
文件大小：22.61MB
文件格式：PDF
更新时间：2021-10-01 04:16:02
集成电路
This session’s high-resolution analog-to-digital converters (ADCs) with 12 to 19b ENOB introduce a number of advanced circuit design techniques to achieve very high performance with low power consumption. While many of the proposed designs use an efficient SAR architecture where possible for moderate resolution, higher performance is consistently enabled by delta-sigma and pipeline architectures. Precision is further enabled by techniques such as hardware re-use, calibration, dynamic element matching, chopping, and correlated double-sampling.