【文件属性】：
文件名称：FPGA--频率计数器
文件大小：2KB
文件格式：RAR
更新时间：2013-10-30 10:05:34
大学EDA的实验课程设计之一
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan_led is
port( clk:in std_logic;
sg:out std_logic_vector(6 downto 0);
bt:out std_logic_vector(7 downto 0));
end;
architecture one of scan_led is
signal cnt8:std_logic_vector(2 downto 0);
signal a:integer range 0 to 15;
begin
p1:process(cnt8)
begin
case cnt8 is
when "000"=>bt<="00000001";a<=1;
when "001"=>bt<="00000010";a<=3;
when "010"=>bt<="00000100";a<=5;
when "011"=>bt<="00001000";a<=7;
when "100"=>bt<="00010000";a<=9;
when "101"=>bt<="00100000";a<=11;
when "110"=>bt<="01000000";a<=13;
when "111"=>bt<="10000000";a<=15;
when others=>null;
【文件预览】：
频率计数器
----32位锁存器.txt(328B)
----8位数码扫描显示器.txt(1KB)
----测频控制电路.txt(578B)
----32位计数器.txt(553B)
网友评论
- 正好用于参考学习频率计数。