文件名称：Clocking Wizard v6.0.pdf
文件大小：3.56MB
文件格式：PDF
更新时间：2021-11-04 19:56:54
IP ClockingWizard
This chapter introduces the Clocking Wizard core and provides related information, including recommended design experience, additional resources, technical support, and ways of submitting feedback to Xilinx. The Clocking Wizard core generates source register transfer level (RTL) code to implement a clocking network matched to your requirements. Both Verilog and VHDL design environments are supported