【文件属性】：
文件名称：Low-voltage LDO Compensation Strategy
文件大小：384KB
文件格式：PDF
更新时间：2013-12-23 18:15:56
LDO Low-voltage Compensation
In this communication, we propose a Miller compensation
technique for low voltage LDO regulators which makes
use of a current amplifier. The analysis shows how to design the
compensation network when no voltage buffer is placed between
the LDO error amplifier and power device and suggests a low
supply voltage circuit topology that allows to compensate with a
reasonably low integrated capacitance, to avoid oscillations due to
the complex-conjugate poles at high output currents and to obtain
acceptable under/overshoots during fast transient load variations.
The designed LDO regulator can work with a supply voltage
down to 1.2V with a drop-out voltage of 200mV at maximum
load current of 100 mA; the integrated compensation capacitance
is 25 pF, the load capacitor being equal to 1 μF. Simulations in
good agreement with the theoretical results are also shown.