文件名称：H5MS2562JFR.pdf
文件大小：1.28MB
文件格式：PDF
更新时间：2017-06-03 03:53:08
H5MS2562JFR
FEATURES SUMMARY ● ●● ●Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle ● ●● ●Mobile DDR SDRAM INTERFACE - x16 bus width - Multiplexed Address (Row address and Column ad- dress) ● ●● ●SUPPLY VOLTAGE - 1.8V device: VDD and VDDQ = 1.7V to 1.95V ● ●● ●MEMORY CELL ARRAY - 256Mbit (x16 device) = 4M x 4Bank x 16 I/O ● ●● ●DATA STROBE - x16 device: LDQS and UDQS - Bidirectional, data strobe (DQS) is transmitted and re- ceived with data, to be used in capturing data at the receiver - Data and data mask referenced to both edges of DQS ● ●● ●LOW POWER FEATURES - PASR (Partial Array Self Refresh) - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - DPD (Deep Power Down): DPD is an optional feature, so please contact Hynix office for the DPD feature ● ●● ●INPUT CLOCK - Differential clock inputs (CK, CK) ● ●● ●Data MASK - LDM and UDM: Input mask signals for write data - DM masks write data-in at the both rising and falling edges of the data strobe