飞思卡尔AD模块

【文件属性】：
文件名称：飞思卡尔AD模块
文件大小：1.18MB
文件格式：RAR
更新时间：2017-10-27 14:31:19
飞思卡尔AD AD模块的飞思卡尔调试程序全部文件： #include /* common defines and macros */ #include "derivative.h" /* derivative-specific definitions */ int i; unsigned char RX_ID[4],RX_DS[8]; unsigned int r[8]; unsigned int temp[2],s; void setbusclock(void) { CLKSEL=0X00; // disengage PLL to system PLLCTL_PLLON=1; // turn on PLL SYNR=0x01; // VCOFRQ[7:6];SYNDIV[5:0] // fVCO= 2*fOSC*(SYNDIV + 1)/(REFDIV + 1) // fPLL= fVCO/(2 × POSTDIV) // fBUS= fPLL/2 // VCOCLK Frequency Ranges VCOFRQ[7:6] // 32MHz <= fVCO <= 48MHz 00 // 48MHz < fVCO <= 80MHz 01 // Reserved 10 // 80MHz < fVCO <= 120MHz 11 REFDV=0x01; // REFFRQ[7:6];REFDIV[5:0] // fREF=fOSC/(REFDIV + 1) // REFCLK Frequency Ranges REFFRQ[7:6] // 1MHz <= fREF <= 2MHz 00 // 2MHz < fREF <= 6MHz 01 // 6MHz < fREF <= 12MHz 10 // fREF > 12MHz 11 // pllclock=2*osc*(1+SYNR)/(1+REFDV)=32MHz; POSTDIV=0x00; // 4:0, fPLL= fVCO/(2xPOSTDIV) // If POSTDIV = $00 then fPLL is identical to fVCO (divide by one). _asm(nop); // BUS CLOCK=16M _asm(nop); while(!(CRGFLG_LOCK==1)); //when pll is steady ,then use it; CLKSEL_PLLSEL =1; //engage PLL to system 分频; } //[设置总线时钟频率为16MHZ] ; // void ATDInit(void) { ATD0CTL2=0x42; // ATD启动，禁止外部触发，允许ATD中断； ATD0CTL3=0x88; // 背景调试模式下继续转换，每1次转换一个转换序列，继续转换； ATD0CTL4=0x01; // 采样时间为 2个时钟周期，转化按10位进行，总分频系数为8； ATD0CTL5=0x20; // 数据右对齐，无符号，单通道采集， } //[AD进行初始化];

【文件预览】：
AD
----bin()
--------Project.abs(326KB)
--------Project.abs.glo(1KB)
--------Project.abs.s19(1KB)
--------Project.map(237KB)
----cmd()
--------P&E_Multilink_CyclonePro_Vppoff.cmd(77B)
--------TBDML_Postload.cmd(59B)
--------P&E_Multilink_CyclonePro_Startup.cmd(59B)
--------Full_Chip_Simulation_Postload.cmd(59B)
--------TBDML_Preload.cmd(60B)
--------TBDML_Reset.cmd(60B)
--------P&E_Multilink_CyclonePro_Reset.cmd(60B)
--------P&E_Multilink_CyclonePro_Erase_unsecure_hcs12xe.cmd(1KB)
--------TBDML_Vppoff.cmd(77B)
--------Full_Chip_Simulation_Reset.cmd(60B)
--------Full_Chip_Simulation_SetCPU.cmd(59B)
--------P&E_Multilink_CyclonePro_Preload.cmd(60B)
--------Full_Chip_Simulation_Startup.cmd(59B)
--------TBDML_Erase_unsecure_hcs12xe.cmd(1KB)
--------P&E_Multilink_CyclonePro_Vppon.cmd(78B)
--------P&E_Multilink_CyclonePro_Postload.cmd(59B)
--------Full_Chip_Simulation_Preload.cmd(60B)
--------TBDML_Startup.cmd(59B)
--------TBDML_Vppon.cmd(78B)
----Project_Data()
--------Standard()
--------CWSettingsWindows.stg(4KB)
----Default.mem(161B)
----MEM_FREE.b2836.20130307.103027A.dump(29KB)
----dengshan_Data()
--------Standard()
--------CWSettingsWindows.stg(4KB)
----C_Layout.hwl(855B)
----prm()
--------Project.prm(16KB)
--------burner.bbl(10KB)
----TBDML.ini(3KB)
----Full_Chip_Simulation.ini(1KB)
----Sources()
--------derivative.h(264B)
--------main.c(6KB)
--------Start12.c(22KB)
--------datapage.c(67KB)
----P&E_Multilink_CyclonePro.ini(4KB)
----AD_Data()
--------Standard()
--------CWSettingsWindows.stg(4KB)
----AD.mcp(58KB)