文件名称：锁相环解码
文件大小：27KB
文件格式：DOC
更新时间：2015-06-16 10:46:52
verilog pll
锁相环解码 verilog语言 if(~reset) begin counter <= 0; m_clk <= 0; end else begin counter <= counter + 1; if(counter == counter_L) begin m_clk <= 1; end else if(counter == counter_H) begin m_clk <= 0; counter <= 0; end end end