【文件属性】：
文件名称：EDP转接芯片介绍
文件大小：2.64MB
文件格式：PDF
更新时间：2020-10-05 11:12:25
EDP，LVDS
2-lane/4-lane eDP @ 1.62/2.7Gbps per lane
FHD to WQXGA (2560*1600) supported
Up to 6dB pre-emphasis
RGB Input
18/24bit RGB Interface
Pixel clock up to 270MHz
SDR/DDR supported
Pin order reversal supported
LVDS Input
Dual-channel 6/8bit LVDS (Sync) interface
400Mbps to 1Gbps per data pair
Built-in termination
Channel and polarity swap supported
Reference Clock
Any freq. between 19MHz and 100MHz
Crystal or single-ended clock input
Built-in 5000ppm SSC generato