【文件属性】:
文件名称:模可变计数器vhdl设计
文件大小:1KB
文件格式:TXT
更新时间:2011-12-28 02:58:12
vhdl设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mod2 is
port(clk,rst,m,en:in std_logic;
cq1:out std_logic_vector(3 downto 0);
cq2:out std_logic_vector(3 downto 0));
end mod2;
architecture behav of mod2 is
signal cql:std_logic_vector(3 downto 0);
signal cqh:std_logic_vector(3 downto 0);
begin
cq2<=cqh;
cq1<=cql;
process(rst,clk,m)
begin
if rst='1' then cql<="0000";cqh<="0000";
elsif clk'event and clk='1' then
if en='1' then
case m is
when '0' =>if cql=9 then cql<="0000";cqh<=cqh+1;
else cql<=cql+1;
end if;
if cqh=2 and cql=2 then cqh<="0000";cql<="0000";
end if;
if cqh>1 and cql>2 then cqh<="0000";cql<="0000";
end if;
when '1' =>if cql=9 then cql<="0000";cqh<=cqh+1;
else cql<=cql+1;
end if;
if cqh=6 and cql=6 then cqh<="0000";cql<="0000";
end if;
end case;
end if;
end if;
end process;
end behav;
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