文件名称:writing testbench using systemverilog
文件大小:2.65MB
文件格式:ZIP
更新时间:2012-03-10 16:25:20
testbench systemverilog
1.What is Verification 2.Verification Technologies 3.The Verification Plan 4.High-Level Modeling 5.Stimulus and Response 6.Architecting Testbenches 7.Simulation Management
【文件预览】:
back-matter.pdf
4High-Level Modeling.pdf
front-matter.pdf
7Simulation Management.pdf
1What is Verification.pdf
6Architecting Testbenches.pdf
2Verification Technologies.pdf
3The Verification Plan.pdf
5Stimulus and Response.pdf