文件名称：ddr sdram controller IP core
文件大小：23KB
文件格式：ZIP
更新时间：2015-04-18 03:10:25
ddr controller IP verilog
ddr sdram controller IP core writen in verilog. source include ddr sdram controller verilog design files and simulation model etc.
【文件预览】：
top.ucf
define.v
glbl.v
top_func.v
string_decode_fn.v
readme.txt
mt46v4m16.v
tb_top.v