文件名称：Static Timing Analysis in VLSI Design.pdf
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更新时间：2022-06-12 08:27:03
Static Timing An VLSI Design
iming,timing,timing!Thatisthemainconcernofadigitaldesigner chargedwithdesigningasemiconductorchip.Whatisit,howisit described,andhowdoesoneverifyit?Thedesignteamofalarge digitaldesignmayspendmonthsarchitectinganditeratingthedesignto achievetherequiredtimingtarget.Besidesfunctionalverification,thetim- ingclosureisthemajormilestonewhichdictateswhenachipcanbere- leasedtothesemiconductorfoundryforfabrication.Thisbookaddresses thetimingverificationusingstatictiminganalysisfornanometerdesigns. Thebookhasoriginatedfrommanyyearsofourworkingintheareaof timingverificationforcomplexnanometerdesigns.Wehavecomeacross manydesignengineerstryingtolearnthebackgroundandvariousaspects ofstatictiminganalysis.Unfortunately,thereisnobookcurrentlyavail- ablethatcanbeusedbyaworkingengineertogetacquaintedwiththede- tailsofstatictiminganalysis.Thechipdesignerslackacentralreferencefor informationontiming,thatcoversthebasicstotheadvancedtimingverifi- cationproceduresandtechniques. Thepurposeofthisbookistoprovideareferenceforbothbeginnersas wellasprofessionalsworkingintheareaofstatictiminganalysis.Thebook T PREFACE xvi isintendedtoprovideablendoftheunderlyingtheoreticalbackgroundas wellasin-depthcoverageoftimingverificationusingstatictiminganaly- sis.Thebookcoverstopicssuchascelltiming,interconnect,timingcalcula- tion,andcrosstalk,whichcanimpactthetimingofananometerdesign.It describeshowthetiminginformationisstoredincelllibrarieswhichare usedbysynthesistoolsandstatictiminganalysistoolstocomputeandver- ifytiming. ThisbookcoversCMOSlogicgates,celllibrary,timingarcs,waveform slew,cellcapacitance,timingmodeling,interconnectparasiticsandcou- pling,pre-layoutandpost-layoutinterconnectmodeling,delaycalculation, specificationoftimingconstraintsforanalysisofinternalpathsaswellas IOinterfaces.Advancedmodelingconceptssuchascompositecurrent source(CCS)timingandnoisemodels,powermodelingincludingactive andleakagepower,andcrosstalkeffectsontimingandnoisearedescribed. Thestatictiminganalysistopicscoveredstartwithverificationofsimple blocksparticularlyusefulforabeginnertothisarea.Thetopicsthenextend tocomplexnanometerdesignswithconceptssuchasmodelingofon-chip variations,clockgating,half-cycleandmulticyclepaths,falsepaths,aswell astimingofsourcesynchronousIOinterfacessuchasforDDRmemoryin- terfaces.Timinganalysesatvariousprocess,environmentandinterconnect cornersareexplainedindetail.Usageofhierarchicaldesignmethodology involvingtimingverificationoffullchipandhierarchicalbuildingblocksis coveredindetail.Thebookprovidesdetaileddescriptionsforsettingup thetiminganalysisenvironmentandforperformingthetiminganalysisfor variouscases.Itdescribesindetailhowthetimingchecksareperformed andprovidesseveralcommonlyusedexamplescenariosthathelpillustrate theconcepts.Multi-modemulti-corneranalysis,powermanagement,as wellasstatisticaltiminganalysesarealsodescribed. Severalchaptersonbackgroundreferencematerialsareincludedintheap- pendices.TheseappendicesprovidecompletecoverageofSDC,SDFand SPEFformats.Thebookdescribeshowtheseformatsareusedtoprovide informationforstatictiminganalysis.TheSDFprovidescellandintercon- nectdelaysforadesignunderanalysis.TheSPEFprovidesparasiticinfor- mation,whicharetheresistanceandcapacitancenetworksofnetsina PREFACE xvii design.BothSDFandSPEFareindustrystandardsandaredescribedinde- tail.TheSDCformatisusedtoprovidethetimingspecificationsorcon- straintsforthedesignunderanalysis.Thisincludesspecificationofthe environmentunderwhichtheanalysismusttakeplace.TheSDCformatis adefactoindustrystandardusedfordescribingtimingspecifications. Thebookistargetedforprofessionalsworkingintheareaofchipdesign, timingverificationofASICsandalsoforgraduatestudentsspecializingin logicandchipdesign.Professionalswhoarebeginningtousestatictiming analysisorarealreadywell-versedinstatictiminganalysiscanusethis booksincethetopicscoveredinthebookspanawiderange.Thisbook aimstoprovideaccesstotopicsthatrelatetotiminganalysis,witheasy-to- readexplanationsandfiguresalongwithdetailedtimingreports. Thebookcanbeusedasareferenceforagraduatecourseinchipdesign andasatextforacourseintimingverificationtargetedtoworkingengi- neers.Thebookassumesthatthereaderhasabackgroundknowledgeof digitallogicdesign.Itcanbeusedasasecondarytextforadigitallogicde- signcoursewherestudentslearnthefundamentalsofstatictiminganalysis andapplyitforanylogicdesigncoveredinthecourse. Ourbookemphasizespracticalityandthoroughexplanationofallbasic conceptswhichwebelieveisthefoundationoflearningmorecomplextop- ics.Itprovidesablendoftheoreticalbackgroundandhands-onguideto statictiminganalysisillustratedwithactualdesignexamplesrelevantfor nanometerapplications.Thus,thisbookisintendedtofillavoidinthis areaforworkingengineersandgraduatestudents. ThebookdescribestimingforCMOSdigitaldesigns,primarilysynchro- nous;however,theprinciplesareapplicabletootherrelateddesignstyles aswell,suchasforFPGAsandforasynchronousdesigns.