msp430 C语言例程

【文件属性】：
文件名称：msp430 C语言例程
文件大小：127KB
文件格式：RAR
更新时间：2014-08-22 09:22:18
msp430 目录（字数限制，不完全） Software Toggle P1.0 Software Toggle P1.0, MCLK = VLO/8 ADC12, Sample A0, Set P1.0 if A0 > 0.5*AVcc ADC12, Using the Internal Reference ADC12, Sample A10 Temp, Set P1.0 if Temp ++ ~2C ADC12, Extend Sampling Period with SHT Bits ADC12, Using an External Reference ADC12, Repeated Sequence of Conversions ADC12, Repeated Single Channel Conversions ADC12, Using 10 External Channels for Conversion ADC12, Sequence of Conversions (non-repeated) ADC12, Sample A10 Temp and Convert to oC and oF Output Buffered SMCLK, ACLK, and MCLK Comparator A, Poll input CA0, result in P1.0 Comparator A, Poll input CA0, CA exchange, result in P1.0 Comparator A, Poll input CA0, result in P1.0 Comparator A, Input to CA0, interrupt triggered DAC12_0, Output 1.0V on DAC0 DAC12_0, Output 2.0V on DAC1 DAC12_0, Output Voltage Ramp on DAC0 DCO Calibration Constants Programmer DMA0, Repeated Burst to-from RAM, Software Trigger DMA0, Repeated single transfer to P1OUT, TACCR2 Trigger DMA0, Repeated single transfer UCA1UART 9600, TACCR2, ACLK DMA0, single transfer Mode UART1 9600, ACLK DMA0, Repeated single transfer to DAC0, Sine Output, TACCR1, DCO DMA2, Rpt'd single transfer to DAC1, 8-Bit Sine, TBCCR2, DCO DMA0/1, Rpt'd single transfer to DAC12_0/1, Sin/Cos, TACCR1, XT2 DMA0, ADC12 A10 single Block Xfer to RAM, TBCCR1, DCO DMA0, ADC12 A10 Block Xfer to Flash, TBCCR1, DCO DMA0/1, ADC12 A10 rpt single transfer Xfer to MPY/RAM, TBCCR1, DCO DMA0/1, rpt single transfer Mode UART1 9600 Auto RX/TX String, ACLK DMA0, Repeated Burst to-from RAM, Software Trigger DMA0, Repeated single transfer to P1OUT, TACCR2 Trigger DMA0, Repeated single transferUCA1UART 9600, TACCR2, ACLK DMA0, single transfer Mode UART1 9600, ACLK DMA0, Repeated single transfer to DAC0, Sine Output, TACCR1, DCO DMA2, Rpt'd single transfer to DAC1, 8-Bit Sine, TBCCR2, DCO DMA0/1, Rpt'd single transfer to DAC12_0/1, Sin/Cos, TACCR1, XT2 DMA0, ADC12 A10 single blocktransfer Xfer to RAM, TBCCR1, DCO DMA0, ADC12 A10 rpt single transfer Xfer to Flash, TBCCR1, DCO msp430x261x_dma_11_IAR.c - (Built with IAR) DMA0/1, ADC12 A10 rpt single transfer Xfer to MPY/RAM, TBCCR1, DCO DMA0/1, Block Mode UART1 9600 Auto RX/TX String, ACLK Flash In-System Programming, Copy SegC to SegD Flash In-System Programming w/ EEI, Copy SegC to SegD Flash In-System Programming w/ EEI, Copy SegD to B&C Basic Clock, Implement Auto RSEL SW FLL Basic Clock, Implement Cont. SW FLL with Auto RSEL Basic Clock, MCLK Configured to Operate from XT2 HF XTAL Basic Clock, MCLK Sourced from HF XTAL XT2, NMI Basic Clock, LPM3 Using WDT ISR, 32kHz ACLK Basic Clock, LPM3 Using WDT ISR, VLO ACLK 16x16 Unsigned Multiply 8x8 Unsigned Multiply 16x16 Signed Multiply 8x8 Signed Multiply 16x16 Unsigned Multiply Accumulate 8x8 Unsigned Multiply Accumulate 16x16 Signed Multiply Accumulate 8x8 Signed Multiply Accumulate Configure RST/NMI as NMI XT2 Oscillator Fault Detection Software Poll P1.3, Set P1.0 if P1.3 = 1 Software Port Interrupt Service on P1.3 from LPM4 Write a byte to Port 1 Write a byte to Port 7 Write a byte to Port 8 Write a word to Port A DCOCLK Biased with External Resistor Rosc SVS, POR @ 2.5V Vcc Timer_A, Toggle P1.0, CCR0 Cont. Mode ISR, DCO SMCLK Timer_A, Toggle P1.0, CCR0 Up Mode ISR, DCO SMCLK Timer_A, Toggle P1.0, Overflow ISR, DCO SMCLK Timer_A, Toggle P1.0, Overflow ISR, 32kHz ACLK Timer_A, Toggle P1.0, CCR0 Up Mode ISR, 32kHz ACLK Timer_A, Toggle P1.0,P1.2 & P2.0 Cont. Mode ISR, 32kHz ACLK Timer_A, Toggle P1.1/TA0, Up Mode, 32kHz ACLK Timer_A, Toggle P1.1/TA0, Up/Down Mode, DCO SMCLK Timer_A, Toggle P1.1/TA0, Up/Down Mode, 32kHz ACLK Timer_A, PWM TA1-2 Up Mode, DCO SMCLK Timer_A, PWM TA1-2, Up Mode, 32kHz ACLK Timer_A, PWM TA1-2, Up/Down Mode, DCO SMCLK Timer_A, PWM TA1-2, Up/Down Mode, 32kHz ACLK Timer_B, Toggle P1.0, CCR0 Cont. Mode ISR, DCO SMCLK Timer_B, Toggle P1.0, CCR0 Up Mode ISR, DCO SMCLK Timer_B, Toggle P1.0, Overflow ISR, DCO SMCLK Timer_B, Toggle P1.0, Overflow ISR, 32kHz ACLK Timer_B, Toggle P1.0, CCR0 Up Mode ISR, 32kHz ACLK Timer_B, PWM TB1-6, Up Mode, 32kHz ACLK USCI_A0 IrDA External Loopback Test, 8MHz SMCLK USCI_A0, SPI 3-Wire Master Incremented Data USCI_A0, SPI 3-Wire Slave Data Echo UUSCI_A0, 115200 UART Echo ISR, DCO SMCLK USCI_A0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz ACLK UUSCI_A0, 9600 UART, SMCLK, LPM0, Echo with over-sampling USCI_A1, Ultra-Low Pwr UART 2400 Echo ISR, 32kHz ACLK USCI_B0 I2C Master RX single bytes from MSP430 Slave USCI_B0 I2C Slave TX single bytes to MSP430 Master USCI_B0 I2C Master TX single bytes to MSP430 Slave USCI_B0 I2C Slave RX single bytes from MSP430 Master USCI_B0 I2C Master TX multiple bytes to MSP430 Slave USCI_B0 I2C Slave RX multiple bytes from MSP430 Master USCI_B0 I2C Master RX multiple bytes from MSP430 Slave USCI_B0 I2C Slave TX multiple bytes to MSP430 Master USCI_B0, SPI 3-Wire Master Incremented Data USCI_B0, SPI 3-Wire Slave Data Echo Basic Clock, VLO-Driven Timer with VLO Compensation WDT, Toggle P1.0, Interval Overflow ISR, DCO SMCLK WDT, Toggle P1.0, Interval Overflow ISR, 32kHz ACLK WDT+ Failsafe Clock, WDT mode, DCO SMCLK Reset on Invalid Address fetch, Toggle P1.0 WDT+ Failsafe Clock, 32kHz ACLK ADC12, Single Channel Extended Sample, TA1 Trigger USCI_B0 to USCI_B1 I2C RX and TX single bytes