文件名称：USB的VHDL实现源码
文件大小：49KB
文件格式：RAR
更新时间：2011-12-14 05:23:57
VHDL
USB的VHDL实现源码 library IEEE; use IEEE.STD_LOGIC_1164.all; package usbTSTPAK is -------------------- component usbTSTctrl port( signal sim: in STD_LOGIC; -- TRUE while simulating signal stim: in STD_LOGIC; -- TRUE to stimulate UUT -- signal clk48: out STD_LOGIC; -- 48MHz clock signal rst: out STD_LOGIC; -- async reset -- signal uut_rxd: out STD_LOGIC; -- UUT rxd pin signal uut_rx0: out STD_LOGIC; -- UUT rx0 pin signal uut_txd: in STD_LOGIC; -- UUT txd pin signal uut_tx0: in STD_LOGIC; -- UUT tx0 pin -- signal tb_xd: in STD_LOGIC; -- testbench xd signal signal tb_x0: in STD_LOGIC; -- testbench x0 signal signal tb_clk: out STD_LOGIC -- testbench clock ); end component;
【文件预览】：
USB的VHDL实现源码
----xspFPGA.vhd(4KB)
----FIRMWARE.HEX(2KB)
----xspCORE.vhd(7KB)
----xspPHY.vhd(2KB)
----usbEP0.vhd(163KB)
----usbTSTPAK.vhd(24KB)
----SRAM.vhd(5KB)
----xspUSB.vhd(4KB)
----xspUC.vhd(2KB)
----transcript(460B)
----TBxsp010pak.vhd(43KB)
----XSP010.vhd(6KB)
----vish_stacktrace.vstf(366B)
----xspCLK.vhd(2KB)
----firmware.a51(26KB)
----xspLED.vhd(2KB)
----TBxsp010.vhd(4KB)