A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL

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文件名称：A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL
文件大小：224KB
文件格式：PDF
更新时间：2013-12-28 13:39:04
A 960-Mb/s/pin Interface for Skew-Tolerant This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peakto- peak jitter of 150 ps and rms jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6-m CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.