文件名称：FIFO_MIG_BASED_AXI：IP-Fi，DDR和MIG c AXI4内存映射接口
文件大小：1.91MB
文件格式：ZIP
更新时间：2024-03-23 19:25:23
SystemVerilog
FIFO_MIG_BASED_AXI：IP-Fi，DDR和MIG c AXI4内存映射接口
【文件预览】：
FIFO_MIG_BASED_AXI-master
----tcl()
--------package_IP.tcl(7KB)
--------example_project.tcl(6KB)
--------run_tests.tcl(11KB)
----wavedrom()
--------write_response.png(44KB)
--------write_address_2.png(55KB)
--------read_end.png(35KB)
--------write_address_1.png(47KB)
--------read_data.png(70KB)
--------write_data.png(90KB)
--------write_address_2(915B)
--------read_address.png(47KB)
--------read_address(742B)
--------block_start.png(50KB)
--------write_data(1KB)
--------read_data(1KB)
--------write_response(752B)
--------read_end(676B)
--------write_address_1(828B)
--------block_start(809B)
----ips()
--------fifo_64x256()
--------fifo_64x512()
--------fifo_128x256()
--------fifo_128x512()
--------fifo_32x128()
--------fifo_32x64()
--------fifo_64x128()
--------fifo_64x64()
--------fifo_128x128()
--------fifo_32x256()
--------fifo_128x64()
--------fifo_32x512()
----microblaze_data()
--------design_example.bit(2.09MB)
--------design_example.mmi(4KB)
--------design_example.xsa(300KB)
--------main.cpp(2KB)
----constraints()
--------timing.xdc(210B)
--------pins.xdc(484B)
--------7A50T_Mig_Pins.xdc(4KB)
--------mig_a.prj(9KB)
----hdl()
--------source()
--------testbench()
--------header()
----yEd()
--------block_design.graphml(206KB)
--------top_design_diagramm.graphml(21KB)
--------algorithm.graphml(76KB)
----docs()
--------docs.docx(937KB)
----.gitignore(394B)