文件名称：fpga串口通信，利用fifo转发
文件大小：122KB
文件格式：7Z
更新时间：2021-04-13 15:46:24
fpga 串口程序
在FPGA平台上，使用verilog语言编写，在quartus ii中编译通过，主要功能是接收串口数据，利用内部的fifo保存数据，然后传输给上位机
【文件预览】：
uart_fifo_design
----uart_fifo_design.fit.smsg(513B)
----uart_fifo_design.qsf(4KB)
----uart_fifo_design.fit.summary(634B)
----uart_fifo_design.cdf(358B)
----uart_fifo_design.sof(821KB)
----fifo_uart_waveforms.html(1KB)
----fifo_uart.qip(366B)
----uart_fifo_design.sim.rpt(168KB)
----uart_fifo_design.map.summary(486B)
----uart_fifo_design.tcl(4KB)
----uart_fifo_design.fit.rpt(196KB)
----src()
--------uart_receiver.v.bak(2KB)
--------uart_fifo_design.v(2KB)
--------key_scan.v(2KB)
--------uart_transfer.v.bak(2KB)
--------fifo_read_write.v(2KB)
--------key_scan.v.bak(2KB)
--------transcript(128B)
--------uart_transfer.v(2KB)
--------uart_fifo_design.v.bak(2KB)
--------uart_receiver.v(2KB)
--------system_ctrl.v(1KB)
--------system_ctrl.v.bak(1KB)
--------clk_generator.v(3KB)
--------clk_generator.v.bak(3KB)
--------fifo_read_write.v.bak(2KB)
----uart_fifo_design.tcl.bak(4KB)
----uart_fifo_design.done(26B)
----uart_fifo_design.sta.rpt(345KB)
----uart_fifo_design.map.rpt(54KB)
----uart_fifo_design.vwf(11KB)
----uart_fifo_design.sta.summary(923B)
----fifo_uart.bsf(3KB)
----fifo_uart_bb.v(5KB)
----uart_fifo_design.qws(591B)
----fifo_uart_wave0.jpg(77KB)
----uart_fifo_design.tan.summary(2KB)
----uart_fifo_design.pof(512KB)
----fifo_uart_wave1.jpg(70KB)
----fifo_uart.v(7KB)
----uart_fifo_design.asm.rpt(8KB)
----uart_fifo_design.qpf(1KB)
----uart_fifo_design.flow.rpt(9KB)
----uart_fifo_design.pin(77KB)
----uart_fifo_design.dpf(239B)